The present invention relates to chemical mechanical polishing of substrates.
An integrated circuit is typically formed on a substrate by the sequential deposition of conductive, semiconductive, or insulative layers on a silicon wafer. One fabrication step involves depositing a filler layer over a non-planar surface, and planarizing the filler layer until the top surfaces of raised structures of the underlying layer are exposed. For example, a conductive filler layer can be deposited on a patterned insulative layer to fill the trenches or holes in the insulative layer. In this case, the portion of the layer that is raised above the bottom of the trenches or holes form the raised pattern. The filler layer is then polished until the raised pattern of the insulative layer is exposed. The process of planarizing the filler layer until the top surfaces of raised structures of the underlying layer are exposed is also referred to as clearing the filler layer. The time required to clear the filler layer will be referred to in this specification as time clearing time. After planarization, the portions of the conductive layer remaining between the raised pattern of the insulative layer form vias, plugs, and lines that provide conductive paths between thin film circuits on the substrate. Copper damascene is one example of the above described fabrication step.
Chemical mechanical polishing (“CMP”) is one polishing technique that can be used for planarization. CMP typically requires that the substrate be mounted on a carrier or polishing head. The exposed surface of the substrate is placed against a rotating polishing disk pad or belt pad. The polishing pad can be either a “standard” pad or a fixed-abrasive pad. A standard pad has a durable roughened surface, whereas a fixed-abrasive pad has abrasive particles held in a containment media. The carrier head provides a controllable load on the substrate to push it against the polishing pad. A polishing slurry, including at least one chemically-reactive agent, and abrasive particles if a standard pad is used, is supplied to the surface of the polishing pad.
Planarization can generally include different polishing processes. For example, planarization can include a first polishing process, for removing the bulk of a filler layer, and a second polishing process, for removing the small amount of the filler layer remaining. The term polishing process refers to a combination of particular actions performed, in a particular sequence, using particular devices and particular materials to remove material. A polishing process can apply one or more polishing techniques.
A polishing process has parameters, exhibits characteristics, and yields results. Parameters of a polishing technique can include, for example, slurry flow rate, force on a abrasive surface being used to polish the substrate, and the radial speed at which the abrasive surface is being rotated. The characteristics of a polishing process can be the manner in which the process removes material, also referred to as the removal profile of the polishing process. A removal profile of a polishing process, which, as described, is a manner in which the polishing process removes material, is different from a thickness profile of a layer, which is the shape of a cross section of the layer. A removal profile is also different from a clearing profile of a substrate, which is the resulting shape of a cross section of a substrate after a filler layer has been cleared. Performing a polishing process on a substrate, that has an initial or pre-polish thickness profile, usually changes the pre-polish thickness profile to a resulting or post-polish thickness profile.
When they are used to manufacture integrated circuits, polishing processes are usually performed in cycles. For example, given a particular polishing process, the actions of this particular process are repeated for each substrate in an assembly line of substrates. A cycle can include one or more polishing processes. For example, given the first and second polishing processes described above, the actions of these processes are repeated for each substrate in the assembly line of substrates.
A clearing profile of a substrate is typically not uniform. When planarization includes a first and a second polishing process, such as, for example, the above described polishing processes, there are three possible causes of the non-uniformity. These are variations in the pre-polish thickness profile of the substrate and variations in the removal profiles of the first and second polishing processes being used to clear a filler layer from the substrate.
A polishing process such as, for example, one that applies CMP, is complete when a substrate layer has been planarized to a desired flatness or thickness, when a filler layer has been cleared, or when a desired amount of material has been removed. The completion or end of the polishing process is sometimes referred to as the polishing end point. In-situ monitoring of the substrate can been performed, for example, with optical or capacitance sensors, in order to detect a polishing endpoint. Other proposed endpoint detection techniques have involved measurements of friction, motor current, slurry chemistry, acoustics and conductivity. One detection technique that has been considered is to induce an eddy current in the metal layer and measure the change in the eddy current as the metal layer is removed.